The present invention relates to power supply circuits of a semiconductor memory and, more specifically, to a control method for achieving low power dissipation.
In this specification, reference will be made to the following publications: Japanese Patent Laid-Open No. 105682/1995 (called the Cited Reference 1; corresponding to U.S. Pat. No. 5,463,588), and Japanese Patent Laid-Open No. 161481/1997 (called the Cited Reference 2).
Semiconductor memories extensively utilize what is known as an on-chip voltage limiter method (i.e., power-down method) whereby the semiconductor chip lowers an externally supplied voltage to generate an internal voltage for use as a power supply. The method is used to reduce power dissipation of circuits or to improve reliability of fine elements in the device. In achieving such objects, voltage limiter circuits (power-down circuits) are utilized to generate the internal supply voltage.
A voltage limiter circuit consumes a steady current so as to maintain an output voltage level even when the semiconductor memory is in standby mode. As a way to reduce power dissipation in the standby state, the Cited Reference 1 proposes a total of eight voltage limiter circuits, i.e., two limiter circuits furnished to each of four memory cell, arrays; and a single, common voltage limiter circuit that is common to all memory cell arrays (FIG. 3 in the Cited Reference 1). The common voltage limiter circuit is constantly in operation. The eight voltage limiter circuits start operating simultaneously when the memory is accessed, and four of the circuits are allowed to remain active upon elapse of a predetermined period of time following the start of the access.
The Cited Reference 2 discloses first and second voltage limiters furnished corresponding to respective first and a second banks, along with a description of operation timings of the limiters. When the first bank is ordered to be activated, the first voltage limiter generates an internal voltage. If the second bank is ordered to be activated while the first bank is still active, the second voltage limiter also generates an internal voltage in cooperation with the first Voltage limiter (FIG. 12 of the Cited Reference 2).